WakeOfAshesPosts: 21,665destroyer of motherfuckers
Dude im not kidding. YOu should get really fucked up sometime. SHits fun. Even drinking alone and engineering shit is awesome. That's what im doing tonight. Let me show you what I've done after 4 Rusty nails and 4 straight scotch's
WakeOfAshesPosts: 21,665destroyer of motherfuckers
It's a transistor layout of a 2-1 MUX. It's liek the lowest logical element you'd have in a computer chip that was being custom made (ASIC instead of FPGA). In your typical CPU you have like 10 Million things like that in there. But usually you only make like a few dozen of those standard cells, and then you glue them all together based on the logic.
The first vertical line is the first input SEL. ANd the next two are the inputs IN1 and IN2. THe last one is the output OUT1. If SEL is a '0' then OUT1 is going to be the same as IN1. If SEL is a '1' then OUT! will be the same as IN2.
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BOOOM!!! 2-1 MUX Bitches! ) )
The first vertical line is the first input SEL. ANd the next two are the inputs IN1 and IN2. THe last one is the output OUT1. If SEL is a '0' then OUT1 is going to be the same as IN1. If SEL is a '1' then OUT! will be the same as IN2.
ANd i did all that shit wasted! \m/